1. Field of the Invention
The present invention relates generally to a driving circuit for display devices such as liquid crystal display devices, electro-luminescence display devices, plasma displays and the like, in which a number of pixel units each of which is made up of three neighboring pixels presenting red color (to be referred to as `R`), green color (to be referred to as `G`) and blue color (to be referred to as `B`), respectively, are arranged matrix-wise so that all the intersection between row-electrodes and column-electrodes are occupied by the pixels. The present invention relates in particular to a driving circuit for the column-electrodes.
2. Description of the Prior Art
For matrix type display devices, it is impossible to display a certain color point in a color picture by a single pixel of a mixed color of the three RGB mixing colors. Therefore, display of a single point in the color picture is effected as a composed color of three pixels, i.e., R-presenting pixel, G-presenting pixel and B-presenting pixel by adjusting intensity for each of RGB colors. For this reason, displaying a certain color point on a screen requires a wider area, i.e., three pixel area for RGB colors in place of a single dot. Therefore, the picture on the screen inevitably becomes rough. To deal with this, it is necessary to improve the fineness of the display pixel matrix so that the area occupied by three pixels on the display screen is reduced to the size as small as a single dot, or if it is impossible to improve the fineness of the display pixel matrix, it is necessary to shift the timings at which pixel signals to be respectively supplied to pixels presenting RGB colors are sampled from respective RGB video signals so that each of the sampled pixel signals may exactly agree with the display position of the pixel on the screen.
Now, description will be made by giving an example of a thin film transistor (TFT) liquid crystal display device with reference to the drawings. FIG. 1 is a block circuit diagram showing a conceptual basic structure of a TFT-employed liquid crystal display device having a display panel 6 in which pixels are provided in matrix-arrangement. With regard to each of TFTs 5, the source S is connected to a column-electrode 2 and the drain D is connected to a pixel electrode 4 whereas the gate G is connected to a row-electrode 1.
A row-electrode driving circuit 7 applies ON-state voltage to a first row-electrode 1a and then applies it to the following row-electrodes 1, one after one. At this time, the ON-state voltage is provided simultaneously for all the gates G of TFTs 5 which are connected to a common row-electrode 1. As a result, all the TFTs 5 connected to the same row-electrode 1 are simultaneously activated or deactivated as analog switches. A column-electrode driving circuit 8 effects samplings from video signals VR, VG and VB, during respective sampling terms (=.tau.) which are determined based on a start pulse SP and a clock signal CKA or CKB given from the outside. Thus sampled pixel signals Sr1, Sg1, Sb1, Sr2 . . . contained in the respective one-dot terms (=.tau.) are provided to corresponding column-electrodes 2r1, 2g1, 2b1, 2r2 . . . each being connected to a pixel presenting R, G or B.
When TFTs 5 on the row-electrode 1a are activated, the channel between the source S and the drain D is made conductive for all the TFTs 5. As a result, the pixel signals Sr1, Sg1, Sb1 and Sr2 . . . are given through column-electrodes 2r1, 2g1, 2b1, 2r2 . . . to respective pixel electrodes 4 of pixels 3R, 3G, 3B, 3R' . . . and held thereby.
Pixels 3 are arranged in all the intersections between row-electrodes 1 and column-electrodes 2 and each pixel 3 is formed of a transparent pixel electrode 4 and a thin film transistor (to be referred to as "TFT" hereinafter) 5. Pixels 3R, 3G and 3B are provided with filters R, G and B (not shown), respectively. Transmittance of liquid crystal (not shown) at each pixel varies in accordance with the pixel signal, e.g., Sr1, Sb1 or Sb1, . . . , applied to the pixel electrode 4. Each of these pixels is adapted to present a predetermined color having adjusted intensity by the liquid crystal with the help of white light emitted from a back light (not shown) passing therethrough.
Here, pixels 3R, 3G and 3B present R, G and B colors, respectively so that `R`, `G` and `B` are denoted in the figure. Other pixels are also designated in the same manner. In this configuration, a mixing color to be displayed by a dot is displayed by three neighboring pixels 3R, 3G and 3B which present the three primary colors R, G and B, respectively and the user senses a composed color from these three pixels. In this case, since each position of the display pixel differs by a length L from the neighboring pixels, the pixel signals Sr1, Sg1 and Sb1 to be given to those pixels must be shifted from one another by one-pixel length. Accordingly, sampling timings of these signals must be shifted from one another by one-dot term (.tau.). The sampling method in which the data for neighboring three pixels are sampled individually and successively is called as three-point successive sampling method and is used widely.
Referring now to the drawings, the three-point successive sampling method will be described. FIGS. 2 and 6 respectively show a block circuit diagram of a column-electrode driving circuit 8 and a timing chart used in the case. FIGS. 4 and 5 respectively show a sampling circuit 20 and an output buffer circuit 21. In FIG. 2, the same components as in described in FIG. 1 are denoted with the same reference numerals and detailed description for those is omitted. Sampling circuits 20a, 20b, 20c, 20d, 20e, 20f, . . . all have an identical circuit structure with that of the sampling circuit 20 shown in FIG. 4. Output buffer circuits 21a, 21b, 21c, 21d, 21e, 21f, . . . all have an identical circuit structure with that of the output buffer circuit 21 shown in FIG. 5.
In FIG. 4, a sampling pulse A supplied to the gate G of a TFT 23 via a terminal 25 represents one of sampling pulses Ar1, Ag1, Ab1, Ar2, Ag2, Ab2, . . . shown in FIG. 2. A video signal V supplied to a terminal 26 represents one of video signals VR, VG and VB shown in FIG. 2. If TFT 23 serving as an analog switch is turned on by the sampling pulse A, the channel between the source S and the drain D becomes conductive and consequently, the video signal V is held by a sampling condenser 24. The sampling circuit 20 outputs the held video signal V as a pixel signal B via a terminal 27 to a next step, i.e., to a terminal 32 of an output buffer circuit 21 (FIG. 5). Here, the pixel signal B represents one of pixel signals Br1, Bg1, Bb1, Br2, Bg2, Bb2, . . . shown in FIG. 2. It should be noted that TFT 23 may be replaced with another element as long as it works as an analog switch.
In FIG. 5, a hold pulse OE which is given to the gate G of a TFT 28 via a terminal 31 is to be provided from a terminal 19 shown in FIG. 2 after the completion of all the sampling operations for one-line period. When the hold pulse OE activates TFT 28 serving as an analog switch, the channel between the source S and drain D is made conductive, and consequently, the pixel signal B supplied to the terminal 32 is held by a hold condenser 29 and amplified by an amplifier 30. The thus amplified signal is outputted as a pixel signal S via a terminal 33 to a next step, i.e., to one of the column-electrodes 2. Here, the pixel signal S represents one of pixel signals Sr1, Sg1, Sb1, Sr2, Sg2, Sb2, . . . . It should be noted that TFT 28 may be replaced with another element as long as it has a function of an analog switch.
In FIG. 2, provided to terminals 12, 13 and 14 are video signals VR, VG and VB, respectively. Terminal 9 is supplied with a start pulse SP shown in FIG. 6(101) and terminal 10 is supplied with a clock signal CKA pulsing periodically at intervals of one-dot term (.tau.) as shown in FIG. 6(102). A pulse width determining circuit 22 receives the start pulse SP to generate a pulse SPA having a predetermined pulse width shown in FIG. 6(103).
D-flip flops DA1, DA2, DA3, DA4, DA5, DA6, . . . sample pulses SPA, QA1, QA2, QA3, QA4, QA5, . . . , respectively, when the clock signal CKA given to terminals CKs rises and generate pulses QA1, QA2, QA3, QA4, QA5, QA6, . . . , respectively, as shown in FIGS. 6(104), (105), (106), (107), (108), and (109), each of which is delayed by .tau. from the pulse immediately before. The thus generated signals are provided to sample hold circuits 20a, 20b, 20c, 20d, 20e, 20f, . . . , respectively.
For instance, since pulses QA1, QA2 and QA3 have different pulse terms shifted by .tau. from one to the next, pixel signals Br1, Bg1 and Bb1 sampled respectively from video signals VR, VG and VB at the rise of pulse QA1, QA2 or QA3, will have video data on different positions shifted by one pixel. Similarly, pixel signals Br1, Bg1, Bb1, Br2, Bg2, Bb2, . . . outputted by sampling circuits 20a, 20b, 20c, 20d, 20e, 20f, . . . will have video data on different positions shifted by one pixel from one to the next. Accordingly, pixel signals Sr1, Sg1, Sb1, Sr2, Sg2, Sb2, . . . provided for column-electrodes 2r1, 2g1, 2b1, 2r2, 2g2, 2b2, . . . by output buffer circuits 21a, 21b, 21c, 21d, 21e, 21f, . . . have video data on different positions shifted by one pixel, or by the length L from one to the next. Since the pixels on the row-electrode 1 which respectively receive the pixel signals Sr1, Sg1, Sb1, Sr2, Sg2, Sb2, . . . simultaneously, are arranged at intervals of the length L, any mismatch will not occur at all when composed picture is observed.
Nevertheless, since the above-described three-point successive sampling method uses the clock signal CKA periodically pulsing at intervals of one-dot term .tau. as shown in FIG. 6(102), the input clock frequency is rather high. Accordingly, if the frequency of the input clock is increased with the augment of the number of the horizontal pixels, the system could bring about unwanted radiation or induce errors in logical operations. Therefore, the three-point successive sampling method is pertinent to only use for driving a display device having a small number of horizontal pixels.
In contrast, in a case where a display device having a large number of horizontal pixels is to be driven, use is made of a sampling method termed as `three-point simultaneous sampling` in which pixel signals Sr, Sg and Sb are sampled at the same timing from video signals VR, VG and VB, respectively. The period of the clock signal CKB used in this case is as long as three-dot term (3.tau.), so that if the input clock frequency is increased with the augment of the number of the horizontal pixels, it is possible to avoid the occurrence of unwanted radiation as well as errors in logical operations.
Japanese Patent Application Laid-Open Hei 3 No.158895, for instance, presents a color matrix display device capable of effecting the three-point simultaneous sampling in order to solve the problems accompanied by the three-point successive sampling method.
The three-point simultaneous sampling method, however, exhibits another defect, namely unnaturalness in the picture. More specifically, despite that positions of neighboring three pixels 3R, 3G, 3B differs by the length L from one to the next, the three samplings are effected simultaneously. As a result, the sampled pixel signals Sr1, Sg1 and Sb1 will be formed from completely identical video information with the shift `0`, thus presenting unnaturalness to the formed picture. To make matters worse, despite that the displaying position of the pixel 3B differs by only the length L from that of the adjoining pixel 3R', there is a 3.tau.-lag between the time at which signal sampling for the pixel 3B is made from the video signal VB and the time at which signal sampling for the pixel 3R' is made from the video signal VR. In other words, video data to be spaced three pixels away or shifted by 3L in length is displayed and observed side by side so that the discontinuity between the two will be inevitably notable.
Now, the three-point simultaneous sampling will be detailed with reference to the drawings. FIGS. 3 and 7 respectively show a block circuit diagram of a column-electrode driving circuit 8 and a timing chart used in the case. FIGS. 4 and 5 show a sampling circuit 20 and an output buffer circuit 21, respectively, to be used for those shown in FIG. 3. In FIG. 3, the same components as in described in FIG. 2 are denoted with the same reference numerals and detailed description for those is omitted.
In FIG. 3, terminal 9 is supplied with a start pulse SP shown in FIG. 7(101) and terminal 10 is supplied with a clock signal CKB pulsing periodically at intervals of three-dot term (3.tau.) as shown in FIG. 7(102). A pulse width determining circuit 22' receives the start pulse SP to generate a pulse SPB having a predetermined pulse width shown in FIG. 7(103).
D-flip flops DB1, DB2, . . . sample pulses SPB, QB1, . . . , respectively when the clock signal CKB given to terminals CKs rises and generate pulses QB1, QB2, . . . as shown in FIGS. 7(105) and (106) each of which is delayed by 3.tau. from the corresponding sampled signal. The pulse QB1 is given as sampling pulses Ar1, Ag1 and Ab1, respectively to three sample hold circuits 20a, 20b and 20c corresponding to three neighboring pixels. Similarly, the pulse QB2 is provided as sampling pulses Ar2, Ag2 and Ab2, respectively to three sample hold circuits 20d, 20e and 20f corresponding to three neighboring pixels. The subsequent pulses are provided in the same manner as above.
Accordingly, since all the three sampling pulses Ar1, Ag1 and Ab1 are synchronized with one another, pixel signals Br1, Bg1 and Bb1 respectively sampled by the sampling circuits 20a, 20b and 20c have data on the same video information. Therefore, despite that the pixel signals Sr1, Sg1 and Sb1 are dependent upon the completely identical video information, the displaying pixels 3R, 3G and 3B neighboring are positioned at intervals of the length L, so that the displayed picture will exhibit unnaturalness as stated above.
Moreover, there is a 3.tau.-lag between the timings of the sampling pulses Ab1 and Ar2, which yields a shift reduced to three pixels between the pixel signal Bb1 sampled by the sampling pulse Ab1 and the pixel signal Br2 sampled by the sampling pulse Ar2. Therefore, the pixel signals Sb1 and Sr2 supplied respectively to the neighboring pixels 3B and 3R' shown in FIG. 1 also includes a shift reduced to three pixels. This is equivalent to a 3L-distance. Accordingly, despite that the display state represented by the pixel signal Sr2 should be placed three pixels away from the display state represented by the pixel signal Sb1, the two pixels in practice are arranged side by side or with only one pixel length L apart, so that the discontinuity between the two will be notable giving unnaturalness to the picture.
Japanese Patent Application Laid-Open Hei 4 No.365288 has presented a sampling method of picture signals in which modification of the three-point successive sampling is made by varying the pulse duty factor of clock so as to realize a three close point sampling that provides similar effects to the simultaneous sampling method. This method, however, cannot completely attain the simultaneous sampling. Besides, since the pulse duty of the clock is varied, some troublesome treatments are required such as, for example, providing a filter in order to take a measure against noise radiation.
As described heretofore, it was necessary to determine which sampling should be made the three-point successive sampling or the three-point simultaneous sampling in the initial stage where the column-electrode driving circuit 8 was designed. Therefore, column-electrode driving circuits 8 were required to be produced individually depending upon a specific usage. As a result, the number of the production steps increases, causing increase in cost. Meanwhile, as the variety of utilities of the display devices is expanded, some users or utilities require relatively high horizontal resolution with a certain number of horizontal pixels on a display screen and some do not require such a high resolution with the same number of the pixels. In such cases, the users wished to select one sampling mode from the two, but it was not allowed in the prior art system. In one word, the apparatus could not be used in any sampling mode other than the mode set at shipping.
When the three-point successive sampling is effected, the clock signal CKA has to have a period of one-dot term .tau. as shown in FIG. 6(102). Therefore, if the frequency of the clock signal CKA is tried to be heightened in order to increase the number of horizontal pixels, unwanted radiation would occur or errors would be made in logic operations. For this reason, it is impossible to realize a high-resolution as long as a driving circuit based on the three-point successive sampling mode is used for a display panel having a large number of horizontal pixels.
A circuit arrangement of both the circuits shown in FIGS. 2 and 3 in parallel requires an extremely large area for the driving circuit, so that it is unfeasible to realize the system in practice.